 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 1/35 l6918 L6918A october 2002 n output current in excess of 100a n ultra fast load transient response n remote sense buffer n integrated 2a gate drivers n 5 bit vid voltage positioning, vrm 9.0 n 0.6% internal reference accuracy n digital 2048 step soft-start n ovp & ocp protections n rdson or rsense current sensing n 1200khz effective switching frequency, externally adjustable n power good output and inhibit n package: so28 applications n high density dc-dc for servers and workstations n supply for high current microprocessors n distributed power description L6918A is a master device that it has to be combined with the l6918,slave, realizing a 4-phases topology, interleaved. the device kit is specifically designed to provide a high performance/high density dc/dc con- version for high current microprocessors and distrib- uted power. each device implements a dual-phase step-down controller with a 180 phase-shift between each phase. a precise 5-bit dac allows adjusting the output volt- age from 1.100v to 1.850v with 25mv binary steps. the high peak current gate drives affords to have high system switching frequency, typically of 1200khz, and higher by external adjustement. the device kit assure a fast protection against ovp, uvp and ocp. an internal crowbar, by turning on the low side mosfets, eliminates the need of external pro- tection. in case of over-current, the system works in constant current mode. so28 ordering numbers: l6918d, L6918Ad l6918dtr, L6918Adtr 5 bit programmable multiphase controller pin connections 1 3 2 4 5 6 7 8 9 18 17 16 15 19 20 10 11 12 13 14 24 23 22 21 25 26 27 28 lgate1 vccdr phase1 fb boot1 ugate1 vsen vcc sgnd comp isen1 pgnds1 fbr fbg sync_in slave_ok sync / adj vprog_in boot2 pgood ugate2 phase2 lgate2 pgnd osc / inh / fault isen2 pgnds2 sync_out l6918 (slave) 1 3 2 4 5 6 7 8 9 18 17 16 15 19 20 10 11 12 13 14 24 23 22 21 25 26 27 28 lgate1 vccdr phase1 fb boot1 ugate1 vprog_out vcc sgnd comp isen1 pgnds1 sync_out slave_ok vid3 vid2 vid1 vid4 boot2 pgood ugate2 phase2 lgate2 pgnd osc / inh / fault isen2 pgnds2 vid0 L6918A ( master)
l6918 L6918A 2/35 L6918A (master) device block diagram l6918 (slave) device block diagram ugate1 current reading i fb to tal cur rent curr ent avg ch1 ocp dac digita l so ft- s tar t logic pwm adaptive anti cros s co nduct i on ch1 ocp 2 phase oscillator pwm1 cu rren t cor rectio n error amplifier ls ls hs vc c hs boo t1 phas e1 lgate1 isen1 pgnds1 pgnd pgnds2 isen2 lgate2 phas e2 ugate2 boo t2 vcc comp fb vsen vid0 vid1 vid2 vid3 vid4 rosc / inh sgnd vccdr vcc dr vcc logic and prote ctions ch2 ocp pwm2 cu rren t cor rectio n ch2 ocp current reading logic pwm adaptive anti cros s co nduct ion pgood synch. circuitry sync_ out slave_ok ugate1 current reading current reading i fb to tal cur rent curr ent avg ch1 ocp dac digita l so ft- s tar t logic pwm adaptive anti cros s co nduct i on logic pwm adaptive anti cros s co nduct i on ch1 ocp 2 phase oscillator pwm1 cu rren t cor rectio n error amplifier ls ls hs vc c hs boo t1 phas e1 lgate1 isen1 pgnds1 pgnd pgnds2 isen2 lgate2 phas e2 ugate2 boo t2 vcc comp fb vsen vid0 vid1 vid2 vid3 vid4 rosc / inh sgnd vccdr vcc dr vcc logic and prote ctions ch2 ocp pwm2 cu rren t cor rectio n ch2 ocp current reading current reading logic pwm adaptive anti cros s co nduct ion logic pwm adaptive anti cros s co nduct ion pgood synch. circuitry sync_ out slave_ok ugate1 current reading i fb to tal cur rent curr ent avg ch1 ocp logic pwm adaptive ant i cross conduction ch1 ocp 2 phase oscillator pwm1 cu rren t cor rection error amplifier ls ls hs vc c hs boo t1 phas e1 lgate1 isen1 pgnds1 pgnd pgnds2 isen2 lgate2 phas e2 ugate2 boo t2 vcc comp fb vsen rosc / inh sgnd vccdr vcc dr vcc logic and protections ch2 ocp pwm2 cu rren t cor rection ch2 ocp current reading logic pwm adaptive anti cross conduct ion pgood sync_ out slav e_ok remote buffer 10 k 10 k 10k vsen fbg fbr 10k vprog_i n sync_i n slave / adj synch. circuitry ugate1 current reading current reading i fb to tal cur rent curr ent avg ch1 ocp logic pwm adaptive ant i cross conduction logic pwm adaptive ant i cross conduction ch1 ocp 2 phase oscillator pwm1 cu rren t cor rection error amplifier ls ls hs vc c hs boo t1 phas e1 lgate1 isen1 pgnds1 pgnd pgnds2 isen2 lgate2 phas e2 ugate2 boo t2 vcc comp fb vsen rosc / inh sgnd vccdr vcc dr vcc logic and protections ch2 ocp pwm2 cu rren t cor rection ch2 ocp current reading current reading logic pwm adaptive anti cross conduct ion logic pwm adaptive anti cross conduct ion pgood sync_ out slav e_ok remote buffer 10 k 10 k 10k vsen fbg fbr 10k vprog_i n sync_i n slave / adj synch. circuitry 3/35 l6918 L6918A absolute maximum ratings thermal data symbol parameter value unit vcc, v ccdr to pgnd 15 v v boot -v phase boot voltage 15 v v ugate1 -v phase1 v ugate2 -v phase2 15 v lgate1, phase1, lgate2, phase2 to pgnd -0.3 to vcc+0.3 v vid0 to vid4 -0.3 to 5 v all other pins to pgnd -0.3 to 7 v v phasex sustainable peak voltage t<20ns @ 600khz 26 v symbol parameter value unit r th j-amb thermal resistance junction to ambient 60 c / w t max maximum junction temperature 150 c t storage storage temperature range -40 to 150 c t j junction temperature range 0 to 125 c p max max power dissipation at tamb=25 c 2w L6918A (master) pin function n. name description 1 lgate1 channel 1 low side gate driver output. 2 vccdr ls mosfet driver supply. 5v or 12v buses can be used. 3 phase1 this pin is connected to the source of the upper mosfet and provides the return path for the high side driver of channel 1. 4 ugate1 channel 1 high side gate driver output. 5 boot1 channel 1 bootstrap capacitor pin. this pin supplies the high side driver. connect through a capacitor to the phase1 pin and through a diode to vcc (cathode vs. boot). 6 vcc device supply voltage. the operative supply voltage is 12v. 7 gnd all the internal references are referred to this pin. connect it to the pcb signal ground. 8 comp this pin is connected to the error amplifier output and is used to compensate the control feedback loop. 9 fb this pin is connected to the error amplifier inverting input and is used to compensate the voltage control feedback loop. a current proportional to the sum of the current sensed in both channel is sourced from this pin (50 m a at full load, 70 m a at the over current threshold). connectin g a resistor r fb between this pin and vsen pin allows pro g rammin g the droop effect. 10 vprog_out reference voltage output used for voltage regulation. this pin must be connected together with the slave device vprog_in pin. filter to sgnd with 1nf capacitor (a total 30nf distributed capacitance is allowed). 11 sync_out synchronization output signal. from this pin exits a square - 50% duty cycle - 5vpp C90 deg phase shifted wave clock signal that the slave device pll locks to. connect this pin to the slave sync_in pin. 12 slave_ok open-drain input/output used for start-up and to manage protections as shown in the timing diagram. internally pulled-up. connect together with other ics slave_ok pin. filter with 1nf capacitor vs. sgnd. l6918 L6918A 4/35 13 isen1 channel 1 current sense pin. the output current may be sensed across a sense resistor or across the low-side mosfet rdson. this pin has to be connected to the low-side mosfet drain or to the sense resistor through a resistor rg in order to program the current intervention for each phase at 140% as follow: where 35 m a is the current offset information relative to the over current condition (offset at oc threshold minus offset at zero load).the net connecting the pin to the sense point must be routed as close as possible to the pgnds1 net in order to couple in common mode any picked-up noise. 14 pgnds1 channel 1 power ground sense pin. the net connecting the pin to the sense point must be routed as close as possible to the isen1 net in order to couple in common mode any picked-up noise. 15 pgnds2 channel 2 power ground sense pin. the net connecting the pin to the sense point must be routed as close as possible to the isen2 net in order to couple in common mode any picked- up noise. 16 isen2 channel 2 current sense pin. the output current may be sensed across a sense resistor or across the low-side mosfet rds on. this pin has to be connected to the low-side mosfet drain or to the sense resistor through a resistor rg in order to program the current intervention for each phase at 140% as follow: where 35 m a is the current offset information relative to the over current condition (offset at oc threshold minus offset at zero load). the net connecting the pin to the sense point must be routed as close as possible to the pgnds2 net in order to couple in common mode any picked-up noise. 17 osc/inh fau lt oscillator switching frequency pin. connecting an external resistor from this pin to gnd, the external frequency is increased according to the equation: connecting a resistor from this pin to vcc (12v), the switching frequency is reduced according to the equation: if the pin is not connected, the switching frequency is 300khz. forcing the pin to a voltage lower than 0.8v, the device stop operation and enter the inhibit state; all mosfets are turned off. 18 to 22 vid0-4 voltage identification pins. these input are internally pulled-up and ttl compatible. they are used to program the output voltage as specified in table 1 and to set the over voltage and power good thresholds. connect to gnd to program a 0 while leave floating to program a 1. 23 pgood this pin is an open collector output and is pulled low if the output voltage is not within the above specified thresholds. it must be connected with the slaves pgood pin. if not used may be left floating. 24 boot2 channel 2 bootstrap capacitor pin. this pin supplies the high side driver. connect through a capacitor to the phase2 pin and through a diode to vcc (cathode vs. boot). 25 ugate2 channel 2 high side gate driver output. 26 phase2 this pin is connected to the source of the upper mosfet and provides the return path for the high side driver of channel 2. 27 lgate2 channel 2 low side gate driver output. 28 pgnd power ground pin. this pin is common to both sections and it must be connected through the closest path to the low side mosfets source pins in order to reduce the noise injection into the device. L6918A (master) pin function (continued) n. name description i ocpx 35 m ar g r sense -------------------------- = i ocpx 35 m ar g r sense -------------------------- = f s 300khz 14.82 10 6 r osc k w () ----------------------------- + = f s 300khz 12.91 10 7 r osc k w () ----------------------------- + = 5/35 l6918 L6918A l6918 (slave) pin function n. name description 1 lgate1 channel 1 low side gate driver output. 2 vccdr ls mosfet driver supply. 5v or 12v buses can be used. 3 phase1 this pin is connected to the source of the upper mosfet and provides the return path for the high side driver of channel 1. 4 ugate1 channel 1 high side gate driver output. 5 boot1 channel 1 bootstrap capacitor pin. this pin supplies the high side driver. connect through a capacitor to the phase1 pin and through a diode to vcc (cathode vs. boot). 6 vcc device supply voltage. the operative supply voltage is 12v. 7 gnd all the internal references are referred to this pin. connect it to the pcb signal ground. 8 comp this pin is connected to the error amplifier output and is used to compensate the control feedback loop. 9 fb this pin is connected to the error amplifier inverting input and is used to compensate the voltage control feedback loop. a current proportional to the sum of the current sensed in both channel is sourced from this pin (50 m a at full load, 70 m a at the over current threshold). connectin g a resistor r fb between this pin and vsen pin allows pro g rammin g the droop effect. 10 vsen connected to the output voltage it is able to manage over & under-voltage conditions and the pgood signal. it is internally connected with the output of the remote sense buffer for remote sense of the regulated voltage. if no remote sense is implemented, connect it directly to the regulated voltage in order to manage ovp, uvp and pgood. 11 fbr remote sense buffer non-inverting input. it has to be connected to the positive side of the load to perform a remote sense. if no remote sense is implemented, connect directly to the output voltage (in this case connect also the vsen pin directly to the output regulated voltage). 12 fbg remote sense buffer inverting input. it has to be connected to the negative side of the load to perform a remote sense. pull-down to ground if no remote sense is implemented. 13 isen1 channel 1 current sense pin. the output current may be sensed across a sense resistor or across the low-side mosfet rds on. this pin has to be connected to the low-side mosfet drain or to the sense resistor through a resistor rg in order to program the current intervention for each phase at 140% as follow: where 35 m a is the current offset information relative to the over current condition (offset at oc threshold minus offset at zero load). the net connecting the pin to the sense point must be routed as close as possible to the pgnds1 net in order to couple in common mode any picked-up noise. 14 pgnds1 channel 1 power ground sense pin. the net connecting the pin to the sense point must be routed as close as possible to the isen1 net in order to couple in common mode any picked-up noise. 15 pgnds2 channel 2 power ground sense pin. the net connecting the pin to the sense point must be routed as close as possible to the isen2 net in order to couple in common mode any picked-up noise. i ocpx 35 m ar g r sense -------------------------- = l6918 L6918A 6/35 16 isen2 channel 2 current sense pin. the output current may be sensed across a sense resistor or across the low-side mosfet rds on. this pin has to be connected to the low-side mosfet drain or to the sense resistor through a resistor rg in order to program the current intervention for each phase at 140% as follow: where 35 m a is the current offset information relative to the over current condition (offset at oc threshold minus offset at zero load). the net connecting the pin to the sense point must be routed as close as possible to the pgnds2 net in order to couple in common mode any picked-up noise. 17 osc/inh fault oscillator switching frequency pin. connecting an external resistor from this pin to gnd, the external frequency is increased according to the equation: connecting a resistor from this pin to vcc (12v), the switching frequency is reduced according to the equation: if the pin is not connected, the switching frequency is 300khz. forcing the pin to a voltage lower than 0.8v, the device stops operation and enters the inhibit state; all mosfets are turned off. the pin is forced high when an over voltage is detected. this condition is latched; to recover it is necessary turn off and on vcc. 18 sync_out output synchronization signal. a 60 phase shift si g nal exits when the device works as a slave while no si g nal exits when the device works as an ad j ustable. 19 sync / adj slave or adjustable operation. connecting this pin to gnd the device becomes an adjustable two-phase controller using an external reference for its regulation. no soft start is implemented in this condition, so it must be performed with external circuitry. the device switches using its internal oscillator according to the frequency set by r osc . leaving this pin floating, the device works as a slave two-phase controller. it uses the reference sourced from the master device and an internal pll locks the synchronization signal sourced from the master device. 20 slave_ok open-drain output used for start-up and to manage protections as shown in the timing diagram. internally pulled-up. connect together with other ics slave_ok pin. filter with 1nf capacitor vs. sgnd. 21 sync_in synchronization input signal locked during the slave operation. connect to the master sync_out pin. 22 vprog_in reference voltage input used for voltage regulation. this pin must be connected together with the others slave (if present) to the vprog_out pin of the master device. filter to sgnd with 1nf capacitor (a total 30nf distributed capacitance is allowed). if the device works as an adjustable (sync/adj to gnd), this is the reference used for the regulation. 23 pgood this pin is an open collector output and is pulled low if the output voltage is not within the above specified thresholds. it must be connected with the masters pgood pin. if not used may be left floating. l6918 (slave) pin function (continued) n. name description i ocpx 35 m ar g r sense -------------------------- = f s 300khz 14.82 10 6 r osc k w () ----------------------------- + = f s 300khz 12.91 10 7 r osc k w () ----------------------------- + = 7/35 l6918 L6918A 24 boot2 channel 2 bootstrap capacitor pin. this pin supplies the high side driver. connect through a capacitor to the phase2 pin and through a diode to vcc (cathode vs. boot). 25 ugate2 channel 2 high side gate driver output. 26 phase2 this pin is connected to the source of the upper mosfet and provides the return path for the high side driver of channel 2. 27 lgate2 channel 2 low side gate driver output. 28 pgnd power ground pin. this pin is common to both sections and it must be connected through the closest path to the low side mosfets source pins in order to reduce the noise injection into the device. electrical characteristcs (vcc=12v10%, tj=0c to 70c unless otherwise specified) symbol parameter test condition min. typ. max. unit vcc supply current i cc vcc supply current hgatex and lgatex open v ccdr =v boot =12v 7.5 10 12.5 ma i ccdr v ccdr supply current lgatex open; v ccdr =12v 2 3 4 ma i bootx boot supply current hgatex open; phasex to pgnd v cc =v boot =12v 0.5 1 1.5 ma power-on turn-on v cc threshold v cc rising; v ccdr =5v 7.8 9 10.2 v turn-off v cc threshold v cc falling; v ccdr =5v 6.5 7.5 8.5 v turn-on v ccdr threshold v ccdr rising; v cc =12v 4.2 4.4 4.6 v turn-off v ccdr threshold v ccdr falling; v cc =12v 4.0 4.2 4.4 v oscillator and inhibit f osc initial accuracy osc = open osc = open; t j =0 c to 125 c 278 270 300 322 330 khz khz f osc,rosc total accuracy r t to gnd=74k w 450 500 550 khz d vosc ramp amplitude 2 v d max maximum duty cycle osc = open 45 50 - % inh inhibit threshold i sink =5ma 0.8 0.85 0.9 v reference and dac only for L6918A (master) v prog_out reference voltage accuracy vid0 to vid4 see table1 -0.6 - 0.6 % i dac vid pull-up current vidx = gnd 4 5 6 m a vid pull-up voltage vidx = open 3.1 - 3.4 v error amplifier dc gain 80 db sr slew-rate comp=10pf 15 v/ m s offset -7 7 mv differential amplifier (remote buffer) only for l6918 (slave) dc gain 1v/v cmrr common mode rejection ratio 40 db input offset fbr=1.100v to1.850v; fbg=gnd -12 12 mv differential current sensing i isen1 , i isen2 bias current i load = 0% 45 50 55 m a l6918 (slave) pin function (continued) n. name description l6918 L6918A 8/35 table 1. vid settings (only for L6918A) i pgndsx bias current 45 50 55 m a i isen1 , i isen2 bias current at over current threshold 80 85 90 m a i fb active droop current i load = 0 0 1 m a i load = 100% 47.5 50 52.5 m a gate drivers t rise hgate high side rise time v bootx -v phasex =10v; c hgatex to phasex=3.3nf 15 30 ns i hgatex high side source current v bootx -v phasex =10v 2 a r hgatex high side sink resistance v bootx -v phasex =12v; 1.5 2 2.5 w t rise lgate low side rise time v ccdr =10v; c lgatex to pgndx=5.6nf 30 55 ns i lgatex low side source current v ccdr =10v 1.8 a r lgatex low side sink resistance v ccdr =12v 0.7 1.1 1.5 w protections pgood upper threshold (v sen / vprog_in) v sen rising 109 112 115 % pgood lower threshold (v sen / vprog_in) v sen falling 87 90 93 % ovp over voltage threshold (v sen / vprog_in) v sen rising 114 117 120 % uvp under voltage trip (v sen / vprog_in) v sen falling 55 60 65 % v pgood pgood voltage low i pgood = -4ma 0.3 0.4 0.5 v vid4 vid3 vid2 vid1 vid0 output voltage (v) vid4 vid3 vid2 vid1 vid0 output voltage (v) 0 0000 1.850 1000 0 1.450 0 0001 1.825 1000 1 1.425 0 0010 1.800 1001 0 1.400 0 0011 1.775 1001 1 1.375 0 0100 1.750 1010 0 1.350 0 0101 1.725 1010 1 1.325 0 0110 1.700 1011 0 1.300 0 0111 1.675 1011 1 1.275 0 1000 1.650 1100 0 1.250 0 1001 1.625 1100 1 1.225 0 1010 1.600 1101 0 1.200 0 1011 1.575 1101 1 1.175 0 1100 1.550 1110 0 1.150 0 1101 1.525 1110 1 1.125 0 1110 1.500 1111 0 1.100 0 1111 1.475 1111 1 shutdown electrical characteristcs (continued) (vcc=12v10%, tj=0c to 70c unless otherwise specified) symbol parameter test condition min. typ. max. unit 9/35 l6918 L6918A four phase reference schematics pgood pgnd pgnds2 isen2 lgate2 phase2 ugate2 boot2 vcc sgnd osc / inh vid0 vid1 vid2 vid3 vid4 isen1 lgate1 phase1 ugate1 boot1 vccdr 6 24 25 26 27 16 15 2 5 4 3 1 13 11 22 21 20 18 19 7 28 23 10 12 vprog_out slave ok 17 rg rg ls2 hs2 l2 c out s1 s0 s3 s2 s4 r g r g ls1 l1 hs1 vin g ndin pgood master L6918A c in fbg pgnd pgnds2 isen2 lgate2 phase2 ugate2 boot2 vcc pgood sync_out sync/adj pgnds1 isen1 lgate1 phase1 ugate1 boot1 vccdr 6 24 25 26 27 16 15 2 5 4 3 1 13 14 22 21 20 18 19 28 23 11 12 vprog_in slave_ok sgnd osc / inh 7 17 r g r g ls4 hs4 l4 r2 r g r g ls3 l3 hs3 slave l6918 fb comp 9 8 r f c f pgnds1 vsen fb comp 10 9 8 r f c f r f fbr sync_out sync_in r fb 14 to slaves pgood cpu l6918 L6918A 10/35 devices description the devices are integrated circuit realized in bcd technology. they provide, in kit, a complete control logic and protections sets for a high performance four-phases step-down dc-dc converter optimized for microprocessors supply and high density dc-dc converters. they are designed to drive n-channel mosfets in an interleaved four-phase synchronous-rectified buck topology. each controller provides a 180 deg phase shift between its two phases and a 90deg phase-shifted synchronization signal is passed from the master to the slave controller that locks the signal through a pll. the resulting four-phases converter synchronized together results in a 90 deg phase shift on each phase, allowing a consistent reduction of the input capacitors ripple current, minimizing also the size and the power losses. the output voltage of the converter can be precisely regulated, programming the master's vid pins, from 1.100v to 1.850v with 25mv binary steps. the reference for the regulation is passed from the master device to the slave device through apposite pin likewise the synchronization signal. each device provides an average current-mode control with fast transient response. they include a 300khz free-running os- cillator externally adjustable up to 600khz, realized in order to multiply by 4 times the equivalent system fre- quency. the error amplifier features a 15mhz gain-bandwidth product and 10v/ m s slew rate that permits high converter bandwidth for fast transient performances. current information is read in all the devices across the lower mosfets r dson or across a sense resistor in fully differential mode. the current information corrects the pwm output in order to equalize the average current carried the two phases of each device. current sharing between the two phases of each device is then limited at 10% over static and dynamic conditions. current sharing between devices is assured by the droop function. the device protects against over-current, with an ocp threshold for each phase, entering in constant current mode. since the current is read across the low side mosfets, the constant current keeps constant the bottom of the inductors current triangular waveform. when an under voltage is detected the slave device latches. the slave device also perform an over voltage protection that disable immediately both devices turning on the lower driver and driving high the fault pin. over load condition are transmitted from the slave device(s) to the master through the slave_ok line. master - slave interactions figure 1. four phase connection with l6918 family master and slave devices are connected together in order to realize four-phase high performance step-down dc/dc converter. four-phase converter is implemented using L6918A master and one l6918 slave devices as shown in figure 1. a communication bus is implemented among all the controllers involved in the regulation. this bus consists in the following lines: C reference (vprog_in / vprog_out pins): unidirectional line. the devices share the reference for the regulation. the reference is programmed through the master device vid pins. it exits from the master through the vprog_out pin and enters the slave device through the vprog_in pin(s). filter externally with at least 1nf capacitor. L6918A l6918 v id 9.0 sync_out vprog_out slave_ok osc sync_in vprog_in slave_ok osc sync_out slave controlle r master controlle r pgood pgood 11/35 l6918 L6918A C clock signal (sync_in / sync_out pins): unidirectional line. a synchronization signal exits from the master device through the sync_out pin with 90 deg phase- shift and enters the slave device through the sync_in pin. the slave device locks that signal through an internal pll for its regulation. an auxiliary synchronization signal exits from the slave through the sync_out. C slave_ok bus (slave_ok pins): bi-directional line. while the supply voltages are increasing, this line is hold to gnd by all the devices. the slave device sets this line free (internally 5v pulled-up) when it is ready for the soft-start. after that this line is freed, the master device starts the soft start (for further details about soft-start, see the relevant sec- tion). during normal operation, the line is pulled low by the slave device if an over / under voltage is de- tected (see relevant section). C pgood pins: pgood pins are connected together and pulled-up. during soft-start, the master device hold down this line while during normal regulation the slave device de-assert the line if pgood has been lost. connections between the devices are shown in figure 1. oscillator the devices have been designed in order to operate on each phase at the same switching frequency of the in- ternal oscillator. so, input and output resulting frequencies are four times bigger. the oscillator is present in all the devices. since the master oscillator sets the main frequency for the regulation, the slave oscillator gives an offset to the slave's pll. in this way the pll is able to lock the synchronization signal that enters from its sync_in pin; it is able to recover up to 15% offset in the synchronization signal fre- quency. it is then necessary to program the switching frequency for all the devices involved in the multi-phase conversion as follow. the switching frequency is internally fixed to 300khz. the internal oscillator generates the triangular waveform for the pwm charging and discharging with a constant current an internal capacitor. the current delivered to the oscillator is typically 25 m a (fsw = 300khz) and may be varied using an external resistor (r osc ) connected be- tween osc pin and gnd or vcc. since the osc pin is maintained at fixed voltage (typ. 1.235v), the frequency is varied proportionally to the current sunk (forced) from (into) the pin considering the internal gain of 12khz/ m a. in particular connecting it to gnd the frequency is increased (current is sunk from the pin), while connecting rosc to vcc=12v the frequency is reduced (current is forced into the pin), according to the following relation- ships: r osc vs. gnd: r osc vs. 12v: note that forcing a 25 m a current into this pin, the device stops switching because no current is delivered to the oscillator. figure 2 shows the frequency variation vs. the oscillator resistor rosc considering the above reported relation- ships. f s 300khz 1.237 r osc k w () ----------------------------- 12 khz m a ----------- - 300khz 14.82 10 6 r osc k w () ----------------------------- + = + = f s 300khz 12 1.237 C r osc k w () ----------------------------- 12 khz m a ----------- - 300khz 12.918 10 7 r osc k w () -------------------------------- C = + = l6918 L6918A 12/35 figure 2. r osc vs. switching frequency digital to analog converter (only for master device L6918A) the built-in digital to analog converter allows the adjustment of the output voltage from 1.100v to 1.850v with 25mv as shown in the previous table 1. the internal reference is trimmed to ensure the precision of 0.6% and a zero temperature coefficient around the 70 c. the internal reference voltage for the regulation is programmed by the voltage identification (vid) pins. these are ttl compatible inputs of an internal dac that is realized by means of a series of resistors providing a partition of the internal voltage reference. the vid code drives a mul- tiplexer that selects a voltage on a precise point of the divider. the dac output is delivered to an amplifier ob- taining the vprog voltage reference (i.e. the set-point of the error amplifier). internal pull-ups are provided for the vid pins (realized with a 5 m a current generator); in this way, to program a logic "1" it is enough to leave the pin floating, while to program a logic "0" it is enough to short the pin to gnd. the voltage identification (vid) pin configuration also sets the power-good thresholds (pgood) and the over/ under voltage protection (ovp/uvp) thresholds. the reference for the regulation is generated into the master device and delivered to the slave device through the vprog_out / vprog_in pins. programming the "11111" vid code, the device enters the nocpu state: both devices keeps all mosfets off and the condition is latched. cycle the power supply to restart operation. moreover, in this condition, the ovp protection is still active into the slave device with a 0.8v threshold. soft start and inhibit at start-up a ramp is generated from the master device increasing its loop reference from 0v to the final value programmed by vid in 2048 clock periods. the same reference is present on the vprog_out pin, producing an increasing loop reference also into the slave device. in this way all the devices involved in the multi-phase conversion start together with the same increasing reference (see figure 3). before soft start, the lower power mos are turned on after that vccdr reaches 2v (independently by vcc val- ue) to discharge the output capacitor and to protect the load from high side mosfet failures. once soft start be- gins, the reference is increased and also the upper mos begins to switch: the output voltage starts to increase with closed loop regulation. at the end of the digital soft start, the power good comparator is enabled and the pgood signal is then driven high (see fig. 3). the under voltage comparator is enabled when the reference voltage reaches 0.8v. the soft-start will not take place, if both vcc and vccdr pins are not above their own turn-on thresholds. the soft-start takes place, and the master device starts to increase the reference, only if the slave_ok bus is at high level. the slave device keeps this line shorted to gnd until it is ready for the start-up while the master keeps this line free before soft-start; anyway, this line is shorted to gnd if vcc and vccdr are not above the turn-on threshold. during normal operation, if any under-voltage is detected on one of the two supplies, the devices are shutdown. 0 1000 2000 3000 4000 5000 6000 7000 0 100 200 300 fr e que nc y ( khz) rosc(k w ) vs. 12v 0 100 200 300 400 500 600 700 800 900 1000 300 400 500 600 frequency (khz) rosc(k w ) vs. gnd 13/35 l6918 L6918A figure 3. soft start forcing the master osc/inh/fault pin to a voltage lower than 0.8v, the devices enter in inhibit mode: all the power mosfets are turned off until this condition is removed. when this pin is freed, the osc/inh/fault pin reaches the band-gap voltage and the soft start begin as previously explained. in inhibit mode the slave device still have both ovp and uvp protection active referring the thresholds to the incoming reference present at the vprog_in pin if this one is greater than 0.8v. otherwise (vprog_in < 0.8v) uvp is disabled and the ovp threshold is fixed at 0.8v. driver section the integrated high-current drivers allow using different types of power mos (also multiple mos to reduce the rdson), maintaining fast switching transition. the drivers for the high-side mosfets use boot pins for supply and phase pins for return. the drivers for the low-side mosfets use vccdrv pin for supply and pgnd pin for return. a minimum voltage of 5v at vccdrv pin is required to start operations of the device. the controller embodies a sophisticated anti-shoot-through sys- tem to minimize low side body diode conduction time so maintaining good efficiency saving the use of schottky diodes. the conduction time is reduced to few nanoseconds assuring that high-side and low-side mosfets are never switched on simultaneously: when the high-side mosfet turns off, the voltage on its source begins to fall; when the voltage reaches 2v, the low-side mosfet gate drive is applied with 30ns delay. when the low-side mos- fet turns off, the voltage at lgate pin is sensed. when it drops below 1v, the high-side mosfet gate drive is applied with a delay of 30ns. if the current flowing in the inductor is negative, the source of high-side mosfet will never drop. to allow the turning on of the low-side mosfet even in this case, a watchdog controller is enabled: if the source of the high-side mosfet don't drop for more than 240ns, the low side mosfet is switched on so al- lowing the negative current of the inductor to recirculate. this mechanism allows the system to regulate even if the current is negative. the boot and vccdrv pins are separated from ic's power supply (vcc pin) as well as signal ground (sgnd pin) and power ground (pgnd pin) in order to maximize the switching noise immunity. the peak current is shown for both the upper and the lower driver of the two phases in figure 4.a 10nf capacitive load has been used. for the upper drivers, the source current is 1.9a while the sink current is 1.5a with v boot -v phase = 12v; sim- ilarly, for the lower drivers, the source current is 2.4a while the sink current is 2a with v ccdr = 12v. ls vprog_out slave_ok v cc pgood sync_out ch1=pgood; ch2=lgatex; ch3=vprog_out; ch4=slave_ok l6918 L6918A 14/35 figure 4. drivers peak current: high side (left) and low side (right) current reading and over current each device involved in the four phase conversion has its own current reading circuitry and over current protec- tion. as a results, the ocp network design for each device must be performed fort half of the maximum output current. the current flowing trough each phase is read using the voltage drop across the low side mosfets r dson or across a sense resistor (r sense ) and internally converted into a current. the transconductance ratio is issued by the external resistor rg placed outside the chip between isenx and pgndsx pins toward the reading points. the full differential current reading rejects noise and allows to place sensing element in different locations with- out affecting the measurement's accuracy. the current reading circuitry reads the current during the time in which the low-side mosfet is on (off time). during this time, the reaction keeps the pin isenx and pgndsx at the same voltage while during the time in which the reading circuitry is off, an internal clamp keeps these two pins at the same voltage sinking from the isenx pin the necessary current (needed if low-side mosfet r dson sense is implemented to avoid absolute maximum rating overcome on isenx pin). the proprietary current reading circuit allows a very precise and high bandwidth reading for both positive and negative current. this circuit reproduces the current flowing through the sensing element using a high speed track & hold tran conductance amplifier. in particular, it reads the current during the second half of the off time reducing noise injection into the device due to the high side mosfet turn-on (see fig. 5). track time must be at least 200ns to make proper reading of the delivered current. this circuit sources a constant 50 m a current from the pgndsx pin and keeps the pins isenx and pgndsx at the same voltage. referring to figure 5, the current that flows in the isenx pin is then given by the following equation: where r sense is an external sense resistor or the r dson of the low side mosfet and rg is the transconductance resistor used between isenx and pgndsx pins toward the reading points; i phase is the current carried by each phase. the current information reproduced internally is represented by the second term of the previous equation as follow: ch3 = hgate1; ch4 = hgate2 ch3 = lgate1; ch4 = lgate2 i isenx 50 m a r sense i phase r g --------------------------------------------- 50 m ai infox + = + = 15/35 l6918 L6918A since the current is read in differential mode, also negative current information is kept; this allow the device to check for dangerous returning current between the two phases assuring the complete equalization between the phase's currents. figure 5. current reading timing (left) and circuit (right) from the current information for each phase, information about the total current delivered ( i fb =ii nfo1 +i info2 ) and the average current for each phase ( i avg =(i info1 +i info2 )/2 ) is taken. i infox is then compared to i avg to give the correction to the pwm output in order to equalize the current carried by the two phases. the transconductance resistor rg can be designed in order to have current information of 25 m a per phase at full nominal load; the over current intervention threshold is set at 140% of the nominal (ii nfox = 35 m a). accord- ing to the above relationship, the over current threshold (i ocpx ) for each phase, which has to be placed at one half of the total delivered maximum current, results: an over current is detected when the current flowing into the sense element is greater than iocp (i infox >35 m a): the device enters in quasi-constant-current operation. the low-side mosfets stays on until iinfo becomes lower than 35 m a skipping clock cycles. the high side mosfets can be turned on with a t on imposed by the control loop at the next available clock cycle and the device works in the usual way until another ocp event is detected. the device limits the bottom of the inductor current triangular waveform. so the average current delivered can slightly increase also in over current condition since the current ripple increases. in fact, the on time increases due to the off time rise because of the current has to reach the i ocp bottom. the worst-case condition is when the duty cycle reaches its maximum value (d=50% internally limited). when this happens, the device works in constant current and the output voltage decrease as the load increase. crossing the uvp threshold causes the slave device to pull down the slave_ok line. all mosfets are turned off and all the devices involved in the reg- ulation stop working. cycle the power supply to restart operation. figure 6 shows the constant current working condition i infox r sense i phase r g --------------------------------------------- = r sense rg 50 m m a i isenx i phase rg lgatex isenx pgndsx i ls1 i ls2 track & hold total current information r g i ocpx r sense 35 m a ----------------------------------------- - = i ocpx 35 m ar g r sense -------------------------- = l6918 L6918A 16/35 figure 6. constant current operation it can be observed that the peak current (ipeak) is greater than the 140% but it can be determined as follow: where vout min is the minimum output voltage (uvp threshold). the device works in constant-current, and the output voltage decreases as the load increase, until the output voltage reaches the under-voltage threshold (vout min ). when this threshold is crossed, all mosfets are turned off, the fault pin is driven high and the device stops working. cycle the power supply to restart operation. the maximum average current during the constant-current behavior results: in this particular situation, the switching frequency results reduced. the on time is the maximum allowed (t onmax ) while the off time depends on the application: over current is set anyway when i infox reaches 35 m a. the full load value is only a convention to work with con- venient values for i fb . since the ocp intervention threshold is fixed, to modify the percentage with respect to the load value, it can be simply considered that, for example, to have on ocp threshold of 170%, this will cor- respond to i infox = 35 m a (i fb = 70 m a). the full load current will then correspond to i infox = 20.5 m a (i fb = 41 m a). integrated droop function the devices use the droop function to satisfy the requirements of high performance microprocessors, reducing the size and the cost of the output capacitor. this method "recovers" part of the drop due to the output capacitor esr in the load transient, introducing a de- pendence of the output voltage on the load current as shown in figure 7, the esr drop is present in any case, but using the droop function the total deviation of the output voltage is minimized. in practice the droop function introduces a static error proportional to the output current that can be represented by an equivalent output resistance r out . since the device has an average cur- rent mode regulation, the information about the total current delivered is used to implement the droop function. this current (equal to the sum of both i infox ) is sourced from the fb pin. connecting a resistor between this pin and vout, the total current information flows only in this resistor because the compensation network between tonmax tonmax i ocpx ipeak i max vout iout (i fb =50 m a) 2i ocpx (i fb =70 m a i max,to uvp droop effect ipeak i ocpx v in vout min C l ------------------------------------- ton max i ocpx v in vout min C l -------------------------------------- 0.5 t + = + = i max tot , 2i max 2i ocpx ipeak i ocpx C 2 ------------------------------------- - + ? ?? = = f 1 ton max t off + ------------------------------------------ = t off l ipeak i ocpx C v out ------------------------------------- - = 17/35 l6918 L6918A fb and comp has always a capacitor in series (see fig. 8). the voltage regulated by each device is then equal to: where i out is the output current of each device (equal to the total load current i load divided by the number of devices n) since i fb depends on the current information about the two phases of each device, the output characteristic vs. load current is given by: where r out is the equivalent output resistance due to the droop function and i out is still the output current of each device (that is the total current delivered to the load i load divided by 2. figure 7. output transient response without (a) and with (b) the droop function figure 8. active droop function circuit the feedback current is equal to 50 m a at nominal full load (i fb = i info1 + i info2 ) and 70 m a at the ocp interven- tion threshold, so the maximum output voltage deviation is equal to: v out vid r fb i fb vid r fb r sense rg --------------------- - i out C = C = v out vid r fb i out vid r fb r sense rg --------------------- - i out vid r fb r sense rg --------------------- - i load 2 --------------- C = C = C = v m ax v m in v no m ( a ) ( b ) esr dr o p esr d ro p v dr o o p ref comp fb to v out total current info (i info1 +i info2 ) v dr oop r fb ref comp fb to v out total current info (i info1 +i info2 ) v dr oop r fb d v o l_intervention +r fb 70 m a = d v full _positive_load +r fb 50 m a = l6918 L6918A 18/35 droop function is provided only for positive load; if negative load is applied, and then iinfox<0, no current is sunk from the fb pin. the device regulates at the voltage programmed by the vid. output voltage monitoring and protection: power good the output voltage is monitored by the slave device through the pin vsen. if it is not within +12/-10% (typ.) of the programmed value, the pgood output is forced low. pgood is always active in the slave device, also dur- ing soft-start. pgood in the master device has the only masking function during soft-start. since the master has not the output voltage sense, it keeps the pgood to gnd during soft-start and after this step it is freed. the slave device provides over-voltage protection: when the voltage sensed by vsen reaches 117% (typ.) of the reference voltage present at the vprog_in pin, the slave device stops switching keeping the ls mosfets on. the fault pin is driven high (5v) and the slave_ok line is pulled low. the master device then stops switching keeping the ls mosfets on, too. since the condition is latched, power supply (vcc) turn off and on is required to restart operations. under voltage protection is also provided and still detected by the slave device. if the output voltage drops be- low the 60% (typ.) of the reference voltage present at the vprog_in pin for more than one clock period, the slave device stops switching turning off all mosfets and pulling down the slave_ok line: the master device stops switching with ls mosfets on. the osc/inh/fault is not driven high in this case. both over voltage and under voltage are active also during soft start (under voltage after than vout reaches 0.8v). during soft-start the reference voltage used to determine the uv threshold is the increasing voltage driv- en by the 2048 soft start digital counter. moreover, ovp is always active, even during inhibit (see relevant section). over / under voltage behavior are shown in figure 9. figure 9. ovp and uvp latch remote voltage sense a remote sense buffer is integrated into the device to allow output voltage remote sense implementation without any additional external components. in this way, the output voltage programmed is regulated between the re- mote buffer inputs compensating motherboard trace losses or connector losses if the device is used for a vrm module. the very low offset amplifier senses the output voltage remotely through the pins fbr and fbg (fbr is for the regulated voltage sense while fbg is for the ground sense) and reports this voltage internally at vsen pin with unity gain eliminating the errors. keeping the fbr and fbg traces parallel and guarded by a power plane re- sults in common mode coupling for any picked-up noise. if remote sense is not required, the output voltage is sensed by the vsen pin connecting it directly to the output voltage. in this case the fbg and fbr pins must be connected anyway to the regulated voltage ls osc slave_ok ls osc slave_ok under voltage latch over voltage latch l6918 L6918A L6918A l6918 19/35 l6918 L6918A input capacitor the input capacitor is designed considering mainly the input rms current that depends on the duty cycle as re- ported in figure. considering the four phase topology, the input rms current is highly reduced comparing with single or dual phase operation. it can be observed that the input rms value is one half of the dual-phase equivalent input current in the worst- case condition that happens for d=1/8, 3/8,5/8 and 7/8. the power dissipated by the input capacitance is then equal to: input capacitor is designed in order to sustain the ripple relative to the maximum load duty cycle. to reach the high rms value needed by the cpu power supply application and also to minimize components cost, the input capacitance is realized by more than one physical capacitor. the equivalent rms current is simply the sum of the single capacitor's rms current. figure 10. input rms current vs. duty cycle. output capacitor since the microprocessors require a current variation beyond 100a doing load transients, with a slope in the range of tenth a/ m s, the output capacitor is a basic component for the fast response of the power supply. dual phase topology reduces the amount of output capacitance needed because of faster load transient re- sponse (switching frequency is doubled at the load connections). current ripple cancellation due to the 180 phase shift between the two phases also reduces requirements on the output esr to sustain a specified voltage ripple. when a load transient is applied to the converter's output, for first few microseconds the current to the load is supplied by the output capacitors. the controller recognizes immediately the load transient and increases the duty cycle, but the current slope is limited by the inductor value. the output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the esl): p rms esr i rms () 2 = 0.50 0.75 0.25 0.50 0.25 single phase dual phase duty cycle (v out /v in ) rms current normalized (i rms /i out ) 4 phase d v out d i out esr = l6918 L6918A 20/35 a minimum capacitor value is required to sustain the current during the load transient without discharge it. the voltage drop due to the output capacitor discharge is given by the following equation: where d max is the maximum duty cycle value. the lower is the esr, the lower is the output drop during load transient and the lower is the output voltage static ripple. inductor design the inductance value is defined by a compromise between the transient response time, the efficiency, the cost and the size. the inductor has to be calculated to sustain the output and the input voltage variation to maintain the ripple current d i l between 20% and 30% of the maximum output current. the inductance value can be cal- culated with this relationship: where f sw is the switching frequency, v in is the input voltage and v out is the output voltage. increasing the value of the inductance reduces the ripple current but, at the same time, reduces the converter response time to a load transient. the response time is the time required by the inductor to change its current from initial to final value. since the inductor has not finished its charging time, the output current is supplied by the output capacitors. minimizing the response time can minimize the output capacitance required. the response time to a load transient is different for the application or the removal of the load: if during the ap- plication of the load the inductor is charged by a voltage equal to the difference between the input and the output voltage, during the removal it is discharged only by the output voltage. the following expressions give approx- imate response time for di load transient in case of enough fast compensation network response: the worst condition depends on the input voltage available and the output voltage selected. anyway the worst case is the response time after removal of the load with the minimum output voltage programmed and the max- imum input voltage available. figure 11. inductor ripple current vs. vout d v out d i out 2 l 2c out v inmin d max v out C () ------------------------------------------------------------------------------------------ - = l v in v out C f sw d i l ----------------------------- - v out v in -------------- = t application l d i v in v out C ----------------------------- - = t removal l d i v out -------------- = figure 12 C inductor ripple current vs. vout 0 1 2 3 4 5 6 7 8 9 0.5 1.5 2.5 3.5 output volta g e [v] inductor ripple [a] l=3 m h, vin=12v l=2 m h, vin=12v l=1.5 m h , vin=12v l=2 m h, vin=5v l=1.5 m h, vin=5v l=3 m h , vin=5v 21/35 l6918 L6918A main control loop the four phases control loop is composed by two dual phases devices that are independent each other. so, the compensation network and the control loop stability of each device don't depend on the other except for the fact that the other converter represents a load for this one. the l6918/a control loop is composed by the current sharing control loop and the average current mode con- trol loop. each loop gives, with a proper gain, the correction to the pwm in order to minimize the error in its regulation: the current sharing control loop equalize the currents in the inductors while the average current mode control loop fixes the output voltage equal to the reference programmed by vid. figure 12 reports the block diagram of the main control loop figure 12. main control loop diagram current sharing (cs) control loop the devices are configured to work in a four synchronized phase application. since the application is composed by two-phase devices that share reference and synchronization signals, the current sharing between the phases is realized in two different steps: 1. sharing between the phases of the same device; 2. sharing between devices. the current sharing between phases of the same device uses the internal current information to correct the pwm signal in order to equalize the current. active current sharing is implemented using the information from tran conductance differential amplifier in an average current mode control scheme. a current reference equal to the average of the read current (i avg ) is internally built; the error between the read current and this reference is converted to a voltage with a proper gain and it is used to adjust the duty cycle whose dominant value is set by the error amplifier at comp pin (see fig. 13). the current sharing control is a high bandwidth control allowing current sharing even during load transients. the current sharing error is affected by the choice of external components; choose precise rg resistor (1% is necessary) to sense the current. the current sharing error is internally dominated by the voltage mismatch of tran conductance differential amplifier between phases; considering a voltage mismatch equal to 2mv across the sense resistor, the current reading error is given by the following equation: where d i read is the difference between one phase current and the ideal current (i max/2 ). for rsense=4m w and imax=40a the current sharing error is equal to 2.5%, neglecting errors due to rg and rsense mismatches. l 1 l 2 + + pwm1 1/5 + - 1/5 i info2 i info1 4/5 z f(s) pwm2 c o fb comp r o error amplifier reference programmed by vid current sharing duty cycle correction r fb d02in1392 d i read i max ------------------- - 2mv r sense i max -------------------------------------- - = l6918 L6918A 22/35 figure 13. current sharing control loop. the current sharing between devices uses the droop function. each device can be modeled with its thevenin equivalent circuit (that is an ideal voltage source equal to the programmed voltage by vids and its related output resistance r out ), while the whole converter is modeled by the same ideal voltage source and an equivalent output resistance r droop =r out /2; considering this modelization reported in figure 14, it can be seen that the recirculating current between devices depends on the accuracy of the regulation. the accuracy of the voltage source is given by the offset of the master error amplifier vos (6mv typ) and de- pends on the ratio between this offset and the output voltage variation with load (r out ,i out ). the mismatch between the regulated voltages causes a converter to source a current that is sunk by the other one. the accu- racy related to droop resistance depends on precision of feedback current of the device i fb , sense resistors r sense , transconductance resistors rg and feedback resistors r fb . the current sharing error (cse) results: considering the external resistors tolerance of 1%, the typical current feedback accuracy of 2.5 m a/50 m a (5%), 4 phases operation, error amplifier offset vos=6mv, droop resistance r droop =1.5m w (r out =2,r droop ) and i load =60a (i out =i load /2), it results: figure 14. equivalent circuit for current sharing error calculation l 1 l 2 + + pwm1 1/5 1/5 i info2 i info1 pwm2 comp v out current sharing duty cycle correction d02in1393 cse d i out i out ---------------- 1 2 -- - vos r out i out ------------------------------- - ? ?? 2 1 2 -- - d i fb i fb ----------- - ? ?? 2 1 2 -- - d r fb r fb -------------- - ? ?? 2 2 2 -- - d r sense r sense ------------------------- - ? ?? 2 4 2 -- - d r g r g ---------- - ? ?? 2 ++ + + o = cse 1 2 -- - 0.006v 1.5m w 60a ---------------------------------- ? ?? 2 1 2 -- - 2.5 m a 50 m a ---------------- ? ?? 2 1 2 -- - 0.01 () 2 2 2 -- - 0.01 () 2 4 2 -- - 0.01 () 2 + +++ 0.062 6.2% () == vid r droop v out r load i load L6918A l6918 v out r out r out r load v prog recirculating current i load i out i out 23/35 l6918 L6918A average current mode (acm) control loop the average current mode control loop is reported in figure 15. the current information i fb sourced by the fb pin flows into r fb implementing the dependence of the output voltage from the read current. the acm control loop gain results (obtained opening the loop after the comp pin): where: C is the equivalent output resistance determined by the droop function; Cz p (s) is the impedance resulting by the parallel of the output capacitor (and its esr) and the applied load ro; Cz f (s) is the compensation network impedance; Cz l (s) is the parallel of the two inductor impedance; C a(s) is the error amplifier gain; C is the acm pwm transfer function where d v osc is the oscillator ramp amplitude and has a typical value of 2v removing the dependence from the error amplifier gain, so assuming this gain high enough, the control loop gain results: with further simplifications, it results: considering now that in the application of interest it can be assumed that ro>>r l ; esr< 25/35 l6918 L6918A power connections. these are the connections where switching and continuous current flows from the input supply towards the load. the first priority when placing components has to be reserved to this power section, minimizing the length of each connection as much as possible. to minimize noise and voltage spikes (emi and losses) these interconnections must be a part of a power plane and anyway realized by wide and thick copper traces. the critical components, i.e. the power transistors, must be located as close as possible, together and to the controller. considering that the "electrical" components re- ported in figure are composed by more than one "physical" component, a ground plane or "star" grounding con- nection is suggested to minimize effects due to multiple connections. fig. 16a shows the details of the power connections involved and the current loops. the input capacitance (cin), or at least a portion of the total capacitance needed, has to be placed close to the power section in order to eliminate the stray inductance generated by the copper traces. low esr and esl capacitors are required. figure 16. power connections and related connections layout guidelines (same for both phases). power connections related. fig.16b shows some small signal components placement, and how and where to mix signal and power ground planes. the distance from drivers and mosfet gates should be reduced as much as possible. propagation delay times as well as for the voltage spikes generated by the distributed inductance along the copper traces are so minimized. in fact, the further the mosfet is from the device, the longer is the interconnecting gate trace and as a consequence, the higher are the voltage spikes corresponding to the gate pwm rising and falling signals. even if these spikes are clamped by inherent internal diodes, propagation delays, noise and potential causes of instabilities are intro- duced jeopardizing good system behavior. one important consequence is that the switching losses for the high side mosfet are significantly increased. for this reason, it is suggested to have the device oriented with the driver side towards the mosfets and the gatex and phasex traces walking together toward the high side mosfet in order to minimize distance (see fig 17). in addition, since the phasex pin is the return path for the high side driver, this pin must be connected directly to the high side mosfet source pin to have a proper driving for this mosfet. for the ls mosfets, the return path is the pgnd pin: it can be connected directly to the power ground plane (if implemented) or in the same way to the ls mosfets source pin. gatex and phasex connections (and also pgnd when no power ground plane is imple- mented) must also be designed to handle current peaks in excess of 2a (30 mils wide is suggested). v in load hs r gate ls r gate hgatex phasex lgatex pgndx c in c out l d c bootx v in load hs ls bootx phasex vcc sgnd c in c out l d +v cc c vcc a. pcb power and ground planes areas b. pcb small signal components placement l6918 L6918A 26/35 figure 17. device orientation (left) and sense nets routing (right). gate resistors of few ohms help in reducing the power dissipated by the ic without compromising the system efficiency. the placement of other components is also important: C the bootstrap capacitor must be placed as close as possible to the bootx and phasex pins to min- imize the loop that is created. C decoupling capacitor from vcc and sgnd placed as close as possible to the involved pins. C decoupling capacitor from vccdr and pgnd placed as close as possible to those pins. this capac- itor sustains the peak currents requested by the low-side mosfet drivers. C refer to sgnd all the sensible components such as frequency set-up resistor (when present) and also the optional resistor from fb to gnd used to give the positive droop effect. C connect sgnd to pgnd on the load side (output capacitor) to avoid undesirable load regulation ef- fect and to ensure the right precision to the regulation when the remote sense buffer is not used. C an additional 100nf ceramic capacitor is suggested to place near hs mosfet drain. this helps in re- ducing noise. C phase pin spikes. since the hs mosfet switches in hard mode, heavy voltage spikes can be ob- served on the phase pins. if these voltage spikes overcome the max breakdown voltage of the pin, the device can absorb energy and it can cause damages. the voltage spikes must be limited by prop- er layout, the use of gate resistors, schottky diodes in parallel to the low side mosfets and/or snubber network on the low side mosfets, to a value lower than 26v, for 20nsec, at fosc of 600khz max. current sense connectio ns. C remote buffer: the input connections for this component must be routed as parallel nets from the fbg/fbr pins to the load in order to compensate losses along the output power traces and also to avoid the pick-up of any common mode noise. connecting these pins in points far from the load will cause a non-optimum load regulation, increasing output tolerance. C current reading: the rg resistor has to be placed as close as possible to the isenx and pgndsx pins in order to limit the noise injection into the device. the pcb traces connecting these resistors to the reading point must be routed as parallel traces in order to avoid the pick-up of any common mode noise. it's also important to avoid any offset in the measurement and to get a better precision, to con- nect the traces as close as possible to the sensing elements, dedicated current sense resistor or low side mosfet r dson . C moreover, when using the low side mosfet r dson as current sense element, the isenx pin is practi- cally connected to the phasex pin. do not connect the pins together and then to the hs source! the device won't work properly because of the noise generated by the return of the high side driver. in this case route two separate nets: connect the phasex pin to the hs source (route together with hgatex) with a wide net (30 mils) and the isenx pin to the ls drain (route to- gether with pgndsx). moreover, the pgndsx pin is always connected, through the rg resistor, to the pgnd: do not connect directly to the pgnd! in this case the device won't work prop- erly. route anyway to the ls mosfet source (together with isenx net). right and wrong connections are reported in figure 18. symmetrical layout is also suggested to avoid any unbalance between the two phases of the converter towards hs mosfet (30 mils wide) towards ls mosfet (30 mils wide) towards hs mosfet (30 mils wide) to ls mosfet (or sense resistor) to regulated output to ls mosfet (or sense resistor) 27/35 l6918 L6918A figure 18. pcb layout connections for sense nets. interconnections between devices. master and slave devices share reference and other signals for the regulation. to avoid noise injection into de- vices, it is recommended to route these nets carefully. C vprog_in / vprog_out: this is the reference for the regulation. it must be routed far away from any noisy trace and guarded by ground traces in order to avoid noise injection into the device. it can be filtered with a 30nf maximum of distributed capacitance vs. signal ground. C slave_ok: this signal is used by the devices for the start-up synchronization and also to commu- nicate uvp from slave to master device. it must be filtered by 1nf capacitor near the pin of each de- vice to avoid the noise to cause false protection's trigger. demo board description the l6918 demo board shows the operation of the device in a four phases application. this evaluation board al- lows output voltage adjustability (1.100v - 1.850v) through the switches s0-s4 and high output current capability. the board has been laid out with the possibility to use up to two d 2 pack mosfets for the low side switch in order to give maximum flexibility in the mosfet choice. the four layers demo board's copper thickness is of 70 m m in order to minimize conduction losses considering the high current that the circuit is able to deliver. demo board schematic circuit is reported in figure 19. several jumpers allow setting different configurations for the device: jp3, jp4 and jp5 allow configuring the remote buffer as desired. simply shorting jp4 and jp5 the remote buffer is enabled and it senses the output voltage on-board; to implement a real remote sense, leave these jumpers open and connect the fbg and fbr connectors on the demo board to the remote load. to avoid using the remote buffer, simply short all the jumpers jp3, jp4 and jp5. local sense through the r7 is used for the regulation. the input can be configured in different ways using the jumpers jp1, jp2 and jp6; these jumpers control also the mosfet driver supply voltage. anyway, power conversion starts from v in and the device is supplied from v cc (see figure 20). not correct correct to phase connection via to gnd plane to hs gate and source to ls drain and source wrong (left) and correct (right) connections for the current reading sensing nets. l6918 L6918A 28/35 figure 19. demo board schematic pgood pgnd pgnds2 is en2 lgate2 phase2 ugate2 boot2 vcc sgnd os c / inh vid0 vid1 vid2 vid3 vid4 is en1 lgate1 phase1 ugate1 boot1 vccdr 6 24 25 26 27 16 15 2 5 4 3 1 13 11 22 21 20 18 19 7 28 23 10 12 vp rog_out slave_ok 17 r25 r24 q7 q8 c26 l4 c32 r30 d9 c28 c11,c13,c51; c46,c47,c52 c14..c23, c35..c44 c24 r21 jp3 r23 s1 s0 s3 s2 s4 r26 r27 q5 l3 q6 c27 d10 c29 vin gndin gndcor e voutcor pgood master L6918A dz1 c31 jp2 jp1 r33 r35 r32 r34 c9,c10; c33,c34 r38 r39 r16 q5a q7a r19 r20 jp5 jp4 fbg pgnd pgnds2 is en2 lgate2 phase2 ugate2 boot2 vcc pgood sync_out sync/adj pgnds1 is en1 lgate1 phase1 ugate1 boot1 vccdr 6 24 25 26 27 16 15 2 5 4 3 1 13 14 22 21 20 18 19 28 23 11 12 vp rog_in slave_ok sgnd os c / inh 7 17 r4 r3 q3 q4 c3 l2 c7 r10 d3 c6 r2 r5 r6 q1 l1 q2 c4 d4 c5 fbg fbr slave l6918 c8 r13 r15 r12 r14 r18 r17 q1a q3a d5 d6 vcc gndcc fb comp 9 8 c48 r29 c25 r31 r28 jp6 pgnds1 vsen fb comp 10 9 8 c1 r8 c2 r9 r7 fbr sync_out sync_in c12 c50 c45 c49 sl/adj r22 c30 c53 r11 c24 14 to slaves pgood r37 to L6918A pin 6 r36 to l6918 pin 6 29/35 l6918 L6918A figure 20. power supply configuration two main configurations can be distinguished: single supply (v cc = v in = 12v) and double supply (v cc = 12v v in = 5v or different). C single supply: in this case jp6 has to be completely shorted. the device is supplied with the same rail that is used for the conversion. with an additional zener diode dz1 a lower voltage can be derived to supply the mosfets driver if logic level mosfet are used. in this case jp1 must be left open so that the hs driver is supplied with v in -v dz1 through bootx and jp2 must be shorted to the left to use v in or to the right to use v in -v dz1 to supply the ls driver through vccdr pin. otherwise, jp1 must be shorted and jp2 can be freely shorted in one of the two positions. C double supply: in this case v cc supply directly the controller (12v) while vin supplies the hs drains for the power conversion. this last one can start indifferently from the 5v bus (typ.) or from other buses allowing maximum flexibility in the power conversion. supply for the mosfet driver can be programmed through the jumpers jp1, jp2 and jp6 as previously illustrated. jp6 selects now v cc or v in depending on the requirements. some examples are reported in the following figures 21 and 22. figure 21. jumpers configuration: double supply vin gndin dz1 jp2 jp1 vcc gndcc jp6 to vcc pin to hs drains (power input) to bootx (hs driver supply) to vccdr pin (ls driver supply) vin = 5v gndin dz1 jp2 jp1 vcc = 12v gndcc jp6 vcc = 12v hs drains = 5v hs supply = 5v vccdr (ls supply) = 5v vin = 5v gndin dz1 jp2 jp1 vcc = 12v gndcc jp6 vcc = 12v hs drains = 5v hs supply = 12v vccdr (ls supply) = 12 v (a) v cc = 12v; v bootx = vccdr = v in = 5v (b) v cc = v bootx = vccdr = 12v; v in = 5v l6918 L6918A 30/35 figure 22. jumpers configuration: single supply pcb and component layout figure 23. pcb and components layouts (dimensions: 10.8mm x 14.5mm) vin = 12v gndin dz1 6.8v jp2 jp1 vcc = open gndcc jp6 vcc = 12v hs drains = 12v hs supply = 5.2v vccdr (ls supply) = 12v vin = 12v gndin dz1 jp2 jp1 vcc = open gndcc jp6 vcc = 12v hs drains = 12v hs supply = 12v vccdr (ls supply) = 12v (a) v cc = v in = vccdr = 12v; v bootx = 5.2v (b) v cc = v in = v bootx = vccdr = 12v component side internal pgnd plane internal sgnd plane solder side 31/35 l6918 L6918A cpu power supply: 12v in ; 1.45v out ; 110a dc considering the high slope for the load transient, a high switching frequency has to be used. in addition to fast reaction, this helps in reducing output and input capacitor. inductance value is also reduced. a switching frequency of 200khz for each phase is then considered allowing large bandwidth for the compen- sation network. considering the high output current, power conversion will start from the 12v bus. C current reading network and over current: since the maximum output current is i max = 110a, the over current threshold has been set to 110a (27.5a x 4) in the worst case (max mosfet temperature). since the device limits the valley of the trian- gular ripple across the inductors, the current ripple must be considered too. considering the inductor core saturation, a current ripple of 10a has to be considered so that the ocp threshold in worst case becomes ocpx = 22a (27.5a-5a). considering to sense the output current across the low-side mosfets rdson (two in parallel to reduce equivalent r dson ), each stb90nf03l has 6.5m w max at 25c that becomes 9.1m w at 100c considering the temperature variation; the resulting transconductance resis- tor rg has to be: C droop function design: considering a voltage drop of 85mv at full load, the feedback resistor r fb has to be: C inductor design: transient response performance needs a compromise in the inductor choice value: the biggest the in- ductor, the highest the efficient but the worse the transient response and vice versa. considering then an inductor value of 1 m h, the current ripple becomes: C output capacitor: ten rubycon mbz (3300 m f / 6.3v / 12m w max esr) has been used implementing a resulting esr of 1.2m w resulting in an esr voltage drop of 52a*1.2m w = 62mv after a 52a load transient. C compensation network: a voltage loop bandwidth of 20khz is considered to let the device fast react after load transient. the r f c f network results: (r8) (c2) further adjustments can be done on the work bench to fit the requirements and to compensate layout parasitic components. rg i ocpx r dson 35 m ----------------- - 22 4.5m 35 m ------------- 2.7k w (r3 to r6; r24 to r27) === r fb 85mv 70 m a ---------------- 1.2k w (r7) == i d vin vout C l ---------------------------- - d fsw ----------- 12 1.4 C 1 m -------------------- - 1.4 12 ------- - 1 200k ------------ - 6.2a (l1, l2) == = r f r fb v os d v in ------------------------------ 5 4 -- - w t l 2r droop esr + () ------------------------------------------------------- 1.2k 2 12 -------------------- 5 4 -- - 20k 2 p 1 m 2 4.5m 2.7 ------------- 1k 1.2m + ? ?? ---------------------------------------------------------- 3.9k w == = c f co l 2 -- - r f ------------------- - 63300 m 1 m 2 ------ - 3.9k ---------------------------------------- - 22nf == = l6918 L6918A 32/35 part list resistors r2, r9, r20, r23, r31, r42 not mounted smd 0805 r3, r4, r5, r6 r24, r25, r26, r27 2.7k 1% smd 0805 r7, r28 1.2k 1% smd 0805 r11, r22 510 smd 0805 r12 to r19 r32, r33, r34, r35, r38, r39 0 smd 0805 r8, r29 3.9k smd 0805 r10, r30 82 smd 0805 r21 10k smd 0805 r36, r37 1m 1% smd 0805 capacitors c1, c48 not mounted smd 0805 c2, c25 47n smd 0805 c24, c30 100n smd 0805 c3, c4, c26, c27 100n smd 0805 c5, c6, c7, c28, c29, c32 1 m smd 0805 c8, c31 10 m smd 1206 c9, c10, c33, c34 10 m or 22 m / 16v tdk multilayer ceramic smd 1206 c11, c13, c46, c47, c51, c52 1800 m / 16v rubycon mbz radial 23x10.5 c12, c45, c49, c50 1n smd 0805 c53 1n smd 0805 c14, c16, c18, c20, c22 c35, c37, c39, c41, c43 3300 m /6.3v rubycon mbz radial 23x10.5 diodes d3, d4, d9, d10 1n4148 sot23 dz1 not mounted minimelf mosfets q1, q1a, q3, q3a, q5, q5a, q7, q7a stb90nf03l stmicroelectronics d2pack q2, q4, q6, q8 stb90nf03l stmicroelectronics d2pack inductors l1, l2, l3, l4 1 m 77121 core / 5 turns 2 x 1.5 mm controllers u2 l6918 stmicroelectronics so28 33/35 l6918 L6918A static performances figure 24 shows the demo board measured efficiency versus load current in steady state conditions without air- flow at ambient temperature. figure 24. system efficiency figure 25 shows the mosfets temperature versus output current in steady state condition without any air-flow or heat sink. it can be observed that the mosfets are under 100c in any conditions. load regulation is also re- ported from 10a to 110a. figure 25. mosfet temperature and load regulation. dynamic performances figure 26 shows the system response to a load transient from 0a to 110a. the output voltage is contained in the 50mv range. additional output capacitors can help in reducing the initial voltage spike mainly due to the esr. figure 26. 110a load transient response. 55 60 65 70 75 80 85 90 0 102030405060708090100110 output current [a] efficiency [%] 30 40 50 60 70 80 90 100 110 0 102030405060708090100110 output current [a] temperature [ o c] hi g h-side mos low-side mos 1.350 1.370 1.390 1.410 1.430 1.450 1.470 0 102030405060708090100110 output current [a] vout [v] l6918 L6918A 34/35 so28 dim. mm inch min. typ. max. min. typ. max. a 2.65 0.104 a1 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 c 0.5 0.020 c1 45 (typ.) d 17.7 18.1 0.697 0.713 e 10 10.65 0.394 0.419 e 1.27 0.050 e3 16.51 0.65 f 7.4 7.6 0.291 0.299 l 0.4 1.27 0.016 0.050 s8 (max.) outline and mechanical data information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan -malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states. http://www.st.com 35/35 l6918 L6918A |
Price & Availability of L6918A
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |